This application claims priority to Japanese Patent Application No. P2000-159544.
1. Field of the Invention
The present invention relates to a semiconductor device having a modulation doped field effect transistor and a manufacturing method thereof, and, more particularly, to a semiconductor device in which a modulation doped field effect transistor having a channel formed in a multi-layered film comprising single-crystal silicon and single-crystal silicon-germanium, and at least one MOSFET or a bipolar transistor, are realized on one identical substrate, and a manufacturing method thereof.
2. Description of the Background
Existing p-type modulation doped field effect transistors (pMODFET), in which a p-channel is formed in a multi-layered film comprising single-crystal silicon and single-crystal silicon-germanium, are described, for example, in Electronics Letters, 1993, vol. 29, p. 486 (xe2x80x9cdocument 1xe2x80x9d). A cross sectional structure of an existing pMODFET is shown in FIG. 45 of document 1.
In FIG. 45, reference numeral 101 denotes a silicon substrate, wherein a buffer layer 102 comprising single-crystal silicon is formed on the silicon substrate 101. A carrier supply layer 103 comprising p-type single-crystal silicon and a spacer layer 104 comprising single-crystal silicon are formed on the buffer layer 102, and a p-type channel layer 105 comprising single-crystal silicon-germanium and a cap layer 106 comprising single-crystal silicon are successively formed. Since the lattice constant of single crystal germanium is larger by about 4% than the lattice constant of single-crystal silicon, the single-crystal silicon-germanium layer undergoes compressive strain by being put between the single-crystal silicon layers. As a result, since it forms a well layer of lower energy relative to holes in a valance band, holes supplied from the carrier supply layer 103 are collected in the channel layer 105 to form a two-dimensional hole gas to conduct transistor operation. After forming gate electrodes 107 and 108, boron ion is selectively implanted to form a source 109 and a drain 110. Then, the periphery of the transistor is etched to form electrodes 111 to the source and the drain.
For pMODFET, an example of using a buffer layer comprising single-crystal silicon-germanium and forming a channel layer of higher germanium content than the buffer layer is also reported, for example, in IEEE Electron Device Letters 1993, vol. 14, p. 205, wherein a buffer layer with a germanium content of 70% is formed, on which a channel layer comprising single crystal germanium is formed between the carrier supply layer and the barrier layer. Improvement for the mobility in the channel is intended by increasing the germanium content as described above.
In the same manner, an existent n-type modulation doped field effect transistor, (nMODFET) in which an n-channel is formed in a multi-layered film comprising single-crystal silicon and single-crystal silicon-germanium, is described, for example, in Electronics Letters, 1992, vol. 28, p. 160. FIG. 46 shows the cross sectional structure of the existent nMODFET.
In FIG. 46, reference numeral 101 denotes a silicon substrate, wherein a buffer layer 112 comprising single-crystal silicon-germanium is formed on the silicon substrate 101. The buffer layer 112 constitutes a virtual substrate having a lattice constant inherent to silicon-germanium at the surface, for which good crystallinity is required on the surface. When single-crystal silicon-germanium is epitaxially grown on a single-crystal silicon substrate, since it tends to grow at an identical atom distance with that in the substrate, the single-crystal silicon-germanium layer undergoes compressive strain and the lattice constant in the grown plane is the same as the lattice constant of single-crystal silicon. Then, it is necessary to positively introduce dislocation for relieving the strain in order to eliminate the effect of single-crystal silicon of the substrate. For example, when the germanium content is changed so as to be 5% on the side of the silicon substrate and 30% on the side of the surface with the thickness of the silicon-germanium layer of 1.5 xcexcm, dislocation can be confined only within the inside of the buffer layer 112 to make the crystallinity favorable at the surface. A second buffer layer 113 comprising single-crystal silicon-germanium and having the same germanium content as that on the surface of the buffer layer 112 is formed on the buffer layer 112 to form a barrier layer to carriers. Then, a channel layer 114 comprising single-crystal silicon, a spacer layer 115 comprising single-crystal silicon-germanium, and a carrier supply layer 116 comprising n-type single-crystal silicon-germanium, are formed. With such a multi-layered film structure, since the single-crystal silicon layer 114 grows with the lattice constant of single-crystal silicon-germanium, it undergoes tensile strain. As a result, the energy to electrons in the conduction band is lowest in the single-crystal silicon channel layer 114, and electrons supplied from the carrier supply layer 116 formed by way of the spacer layer 115 are stored in the channel layer 115 to form two-dimensional electron gas. A cap spacer layer 117 comprising single-crystal silicon-germanium, and a cap layer 118 comprising single-crystal silicon as the surface protection film, are formed on the surface. Gate electrodes 119 and 120 are formed, and a source 111 and a drain 112 are formed by implantation of phosphorus ion. Finally, by etching the periphery of the transistor, the multi-layered film comprising the single-crystal silicon and single-crystal silicon-germanium as the intrinsic region of the transistor, is fabricated into an island shape, and electrodes 123 to the source and the drain are formed adjacent to the island shape.
Further, nMODFET and pMODFET formed simultaneously in the multi-layered film of single-crystal silicon and single-crystal silicon-germanium in a complementary type is described, for example, in IEEE Transactions on Electron Devices, 1996, vol. 43, p. 1224. FIG. 47 shows a cross sectional shape of the existent complementary modulation doped field effect transistor (cMODFET).
In FIG. 47, reference numeral 101 denotes a silicon substrate, and a buffer layer 124 comprising p-type single-crystal silicon-germanium is formed on the silicon substrate 101. A virtual substrate of satisfactory crystallinity with the lattice constant being the same as that of the single-crystal silicon-germanium layer is formed by relaxing the strain due to the difference of the lattice constant between the silicon substrate 101 and the buffer layer 124 only at the inside of the buffer layer 124. An n-well 125 is formed by ion implantation of n-type dopant only in the region of the forming pMODFET. On the buffer layer 124, are successively laminated a spacer layer 126 comprising single-crystal silicon-germanium having the same germanium content as that of the buffer layer, an n-type carrier supply layer 127 comprising n-type single-crystal silicon-germanium also having the same germanium content, a second spacer layer 128 comprising single-crystal silicon-germanium, an n-type channel layer 129 comprising single-crystal silicon, and a p-type channel layer 130 comprising single-crystal silicon-germanium with a higher germanium content than that on the surface of the buffer layer 124. After covering the surface with a cap layer 131 comprising single-crystal silicon and a silicon oxide film 132, a gate electrode 133 is formed. Using the gate electrode as a mask, a p-type dopant is ion implanted into the region for forming the pMODFET deeper than the p-type channel layer 130, to form a source 134 and a drain 135 of pMODFET, while n-type dopant is ion implanted in the region forming nMODFET deeper than the n-type channel layer 129, to form a source 136 and a drain 137 of nMODFET.
Further, a field effect transistor (FET) forming a channel layer by selective epitaxial growth is described, for example, in Japanese Patent Laid-Open Hei 5-74812. FIG. 48 shows a cross sectional structure of this existent FET.
In FIG. 48, a reference numeral 101 denotes a silicon substrate, and a field oxide film 138 is formed on the silicon substrate 101. A high concentration n-type polycrystalline silicon layer 139, and a gate isolation insulation film 140, are selectively formed on the field oxide film 138, and an opening is disposed in a gate region. A silicon nitride film 141 is formed on the side wall of the opening, and the field oxide film 138 is side-etched to form an overhang of the high concentration n-type polycrystalline silicon 139. Since the silicon substrate 101 is exposed at the bottom of the opening, a channel layer 142 comprising single-crystal silicon-germanium is formed therein and, at the same time, a polycrystalline silicon-germanium layer 143 is deposited from the overhang bottom of the high concentration n-type polycrystalline silicon 139. Then, by selectively forming a single-crystal silicon layer 144 and a polycrystalline silicon layer 145 simultaneously and selectively, source and drain lead electrodes, and a channel layer 142 comprising high concentration n-type polycrystalline silicon, are automatically joined. After selectively forming an insulation film 146 on the side wall of the opening, a single-crystal silicon layer is epitaxially grown, and source and drain take out portions are opened to the gate isolation insulation film 140 and, finally, electrodes 148 are formed.
In a MODFET in which the channel layer is formed utilizing the heterostructure of single-crystal silicon and single-crystal silicon-germanium, a relatively thick buffer layer is necessary for relaxing the strain of silicon-germanium. In the existent MODFET described hereinabove, since a buffer layer or a multi-layered film comprising silicon and silicon-germanium is formed over the entire surface of the wafer, it is necessary to remove the buffer layer and the multi-layered film for mounting together with MOSFET or bipolar transistor in the method of the prior art. FIG. 49 and FIG. 50 show the result of a study on the process flow in a case of mounting an existent pMODFET with a silicon nMOSFET on one identical substrate. A p-well 151 and an n-well 152 are formed each by ion implantation to a portion of a silicon substrate 150 (refer to FIG. 49(a)). Then, a buffer layer 153 comprising a single-crystal silicon-germanium layer and a multi-layered film 154 comprising single-crystal silicon and single-crystal silicon-germanium, is epitaxially grown on the entire surface of the silicon substrate 150 (refer to FIG. 49(b)). In this case, since the single-crystal silicon surface is exposed on the entire surface of the silicon substrate 150, the buffer layer 153 and the multi-layered film 154 are grown as a single crystal layer for the entire surface. Then, the buffer layer 153 and the multi-layered film 154 are removed while leaving a region for forming the p-MODFET. In this case, a step between nMOSFET and pMODFET corresponds to the thickness of the buffer layer 153 and the multi-layered film 154 of silicon and silicon-germanium of pMODFET, plus a step formed to the silicon substrate 150 by etching (refer to FIG. 49(c)).
Then, a gate insulation film 155, a gate electrode 156, and a gate side wall insulation film 157 are formed to pMODFET, and a gate insulation film 158, a gate electrode 159, and a gate side wall insulation film 160 are formed to nMOSFET (refer to FIG. 50(a)). Finally, 1)-type dopant is selectively ion implanted to form a source 161 and a drain 162 of pMODFET, and n-type dopant is selectively ion implanted to form a source 163 and a drain 164 of nMOSFET (refer to FIG. 50(b)).
Further, the result of study on the process flow in a case using a field insulation film and a device isolation insulation region is shown in FIG. 51 and FIG. 52. A field insulation film 165 in a region other than the region forming an intrinsic region for nMOSFET and pMODFET is formed on a silicon substrate 150, and a device isolation insulation film 166 is formed for isolation of the transistors (refer to FIG. 51(a)). Then, p-type and n-type dopants are ion implanted to the regions for forming nMOSFET and pMODFET, to form a p-well 151 and an n-well 152 respectively (refer to FIG. 51(b)). Then, a buffer layer 153 and a multi-layered film 154 comprising single-crystal silicon and single-crystal silicon-germanium are formed on the entire surface of the substrate by epitaxial growth. In this process, a multi-layered film of a single crystal silicon-germanium layer and a single-crystal silicon layer is formed on the silicon substrate, and a multi-layered film of a polycrystalline silicon-germanium layer and a polycrystalline silicon layer are formed on the field insulation film 165 and the device isolation insulation film 166 (refer to FIG. 51(c)). In the region forming nMOSFET, since the surface of the silicon substrate 150 has to be exposed, the multi-layered film 154 comprising silicon and silicon-germanium and the buffer layer 153 are removed while leaving the region forming pMODFET (refer to FIG. 52(d)). After forming a gate insulation film 155, a gate electrode 156 and a gate side wail insulation film 157 to pMODFET, and forming a gate insulation film 158, a gate electrode 159 and a gate side wall insulation film 160 to nMOSFET, p-type dopant is selectively ion implanted to form a source 161 and a drain 162 of pMODFET, and n-dopant is selectively ion implanted to form a source 163 and a drain 164 of nMOSFET (refer to FIG. 52(b)). As the result, the step between pMODFET and nMOSFET corresponds substantially to the thickness of the buffer layer 153 and the multi-layered film 154 comprising silicon amid silicon-germanium.
As can be seen from the processes hereinabove, when MODFET and other devices, such as a MOSFET, are mounted together on one identical substrate, a step at least for the thickness of the buffer layer and the multi-layered film comprising silicon and silicon-germanium is formed by the removal of the region other than the intrinsic region for MODFET. If the step increases, it results in a problem upon forming a pattern for gate electrodes or interconnections by photolithography, in that the focal point does not align and the pattern can be resolved depending on the wavelength of light and the pattern size used for exposure. In a case of using i-ray at a wavelength of 365 nm, since the focal depth is about 1.7 xcexcm for the resolution of a pattern with a minimum size of 0.5 xcexcm, and the focal depth is about 1.0 xcexcm for the resolution of a pattern with a minimum size of 0.2 xcexcm, the size for the gate has to be increased if a step such as that hereianbove is formed. Accordingly, this results in a difficulty for shortening the gate length, thereby bringing about a problem that high performance of transistors can not be attained. Further, when other devices are prepared after forming the buffer layer and the multi-layered film comprising silicon and silicon-germanium in MODFET, since the amount of heat treatment increases in the deposition of the insulation film or the like, the dopant diffuses from the carrier supply layer to the channel layer. As a result, since carriers scatter against dopant ions during operation of the transistor, a difficulty in increasing the operation speed and decreasing noise occurs. On the contrary, when MODFET is formed to a substrate on which MOSFET or bipolar transistor has been previously formed, when a thick buffer layer deposited on the entire surface of the substrate is removed, it results in a problem that damage due to etching applied to the previously formed device deteriorates device performance. As a counter measure, when a protection film to etching is formed, since steps such as deposition of the protection film, removal of the protection film in the region for forming MODFET and formation of an opening to the protection film for contact are additionally required, the number of steps increases, thereby dramatically increasing the cost.
Therefore, the need exists for a technique to reduce the resulting step size in MODFET formation, and to thereby relieve the problem of higher than desired effective gate length which limits transistor performance. It is also desirable to reduce the heat treatment used in devices other than MODFETs, and to thereby reduce the resulting dopant diffusion which limits MODFET device speed and increases device noise. Also, it is desirable to reduce damage and resulting performance loss which occurs during the steps of deposition and removal of protection films in formation of devices other than MODFETs, thereby improving MODFET performance and lowering costs.
The present invention is directed to a semiconductor device in which a modulation doped field effect transistor having a channel formed in a multi-layered film comprising single-crystal silicon and single-crystal silicon-germanium, and at least one MOSFET or a bipolar transistor, are realized on one identical substrate, and a manufacturing method thereof, wherein the step between each of the device forming regions on the substrate is small and the amount of heat treatment is reduced, so that high speed operation and reduction of noise is possible, and which one substrate device combination can be manufactured at a high throughput (yield).
In accordance with an embodiment of the present invention, the step between each of the devices can be eliminated, even in a case of mounting MOSFET and MODFET on one identical semiconductor substrate, by forming a groove to a semiconductor substrate and burying an intrinsic region of a modulation doped field effect transistor (MODFET) in the groove, so that gate electrodes or interconnections can be formed collectively in each of device forming regions with a reduced pattern size, without causing the problems in the photolithography described hereinabove.
Further, after forming the intrinsic region of MODFET, since the gate insulation film, the gate electrode and the like can be formed to each of the devices in one identical step, diffusion of dopant from the carrier supply layer to the channel layer can be suppressed, without increasing the amount of unnecessary heat treatment to increase the operation speed and decrease the noise of MODFET. Further, since the buffer layer is formed in the groove of the semiconductor substrate by selective growth while covering the portion other than the lateral side of the groove and the MOD-forming region with an insulation film, there is no requirement for removing the buffer layer in other device forming regions, and degradation of characteristics of other devices can be avoided.
Further, since a channel layer utilizing the carrier confinement effect by a heterojunction is disposed in the multi-layered film comprising single-crystal silicon and single-crystal silicon-germanium, and doping is not conducted to the channel layer but only to the carrier supply layer isolated by the spacer layer in the intrinsic region of MODFET, the carriers do not scatter against dopant ions, so that mobility of carriers can be improved. Further, since the channel is disposed at the heterojunction boundary, scattering with the boundary level caused by crystal defects is not formed by forming the heterojunction having good crystallinity, so that noise of MODFET can be reduced.
Further, since the channel is formed in the single-crystal silicon-germanium layer undergoing compressive strain in pMODFET and in the single-crystal silicon layer undergoing tensile strain in nMODFET, the energy level is divided due to the effect of strain to decrease interband scattering, so that mobility of carriers in the channel can be increased.
In a case wherein a silicon-germanium hetero bipolar transistor (SiGeHBT) and a modulation doped field effect transistor (MODFET) are mounted together on one identical semiconductor substrate, the same effect as in a case of mounting MOSFET together described hereinabove can be obtained by forming a plurality of grooves for each of the devices in a semiconductor substrate and burying the collector layer of SiGeHBT and the buffer layer of MODFET respectively into the grooves. Those and other advantages and benefits of the present invention will become apparent from the detailed description of the invention hereinbelow.